https://r0tbyt3.dev/tags/architectures/Recent content in Architectures on Jesus OsegueraHugoen-ushttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/Arm M-profile Arm M-profile - the family of Arm processor cores designed for embedded and microcontroller applications, including the Cortex-M series with its NVIC, MPU, and TrustZone-M security extensions. Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns NVIC TrustZone-M Related Links: Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/boot-flow-on-cortex-m/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/boot-flow-on-cortex-m/Boot Flow on Cortex-M Boot Flow on Cortex-M - the sequence of steps from power-on through reset vector fetch, stack pointer initialization, and startup code execution that brings a Cortex-M device to its main application. Related Links: Exceptions Interruptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/bus-fabrics-and-on-chip-interconnects/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/bus-fabrics-and-on-chip-interconnects/Bus Fabrics and On-Chip Interconnects Bus Fabrics and On-Chip Interconnects - the internal communication infrastructure of a SoC that connects the CPU, memory, and peripherals, including AHB, APB, AXI, and crossbar fabrics. Related Links: Arm M-profile CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/CPU Core Concepts CPU Core Concepts - fundamental principles of processor design relevant to embedded systems, including instruction set architectures, pipeline stages, and privilege levels. ISA Privilege Levels Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/Embedded Systems Architectures Embedded Systems Architectures - the different approaches to designing and structuring embedded systems, including single-core, multi-core, and heterogeneous architectures. Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single-Core vs Multi-Core Architectures Related Links: C Language for Embedded Systems Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Hardware Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/exceptions/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/exceptions/Exceptions Exceptions - synchronous and asynchronous events on Cortex-M that transfer control to exception handlers, including faults, SVC calls, and system-level exceptions. Related Links: Boot Flow on Cortex-M Interruptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/harvard/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/harvard/Harvard Harvard - a processor memory architecture that uses separate buses for instruction and data memory, enabling simultaneous fetches and improving throughput in embedded applications. Related Links: Von Neumannhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/heterogeneous-socs-and-co-processors/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/heterogeneous-socs-and-co-processors/Heterogeneous SoCs and Co-processors Heterogeneous SoCs and Co-processors - system-on-chip designs that integrate multiple processor types (such as Cortex-M and Cortex-A), DSPs, or hardware accelerators to balance performance and power efficiency. Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/interruptions/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/interruptions/Interruptions Interruptions - hardware interrupt signals on Cortex-M that trigger IRQ handlers via the NVIC, including priority management, nesting, and tail-chaining behavior. Related Links: Boot Flow on Cortex-M Exceptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/isa/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/isa/ISA ISA - the Instruction Set Architecture defining the set of operations a processor can execute, including encoding formats, addressing modes, and the programmer-visible register model. Related Links: Privilege Levelshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/Memory Architecture Memory Architecture - the organization of instruction and data memory in embedded processors, including the distinctions between Harvard and Von Neumann architectures and their trade-offs. Harvard Von Neumann Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/mpu-usage-patterns/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/mpu-usage-patterns/MPU Usage Patterns MPU Usage Patterns - common configurations of the Cortex-M Memory Protection Unit to enforce privilege separation, protect stack regions, and prevent unauthorized memory access. Related Links: Boot Flow on Cortex-M Exceptions Interruptions NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/nvic/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/nvic/NVIC NVIC - the Nested Vectored Interrupt Controller on Cortex-M that manages interrupt priority, enabling, pending state, and vectored dispatch to handler functions. Related Links: Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/platform-interrupt-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/platform-interrupt-architecture/Platform Interrupt Architecture Platform Interrupt Architecture - the RISC-V PLIC and CLINT interrupt controllers that route external and timer interrupts to harts with configurable priority and threshold settings. Related Links: PMP and Isolation Privilege Model and Trap Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/pmp-and-isolation/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/pmp-and-isolation/PMP and Isolation PMP and Isolation - the RISC-V Physical Memory Protection unit used to restrict memory access by privilege level, enabling isolation between firmware components and sandboxing of untrusted code. Related Links: Platform Interrupt Architecture Privilege Model and Trap Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/power-and-clock-domain-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/power-and-clock-domain-architecture/Power and Clock Domain Architecture Power and Clock Domain Architecture - the organization of clock trees and power domains within a SoC, including clock gating, domain isolation, and power management controller design. Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/privilege-levels/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/privilege-levels/Privilege Levels Privilege Levels - the hardware-enforced execution modes (such as privileged and unprivileged) that control access to protected instructions, registers, and memory regions. Related Links: ISAhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/privilege-model-and-trap-handling/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/privilege-model-and-trap-handling/Privilege Model and Trap Handling Privilege Model and Trap Handling - the RISC-V privilege levels (Machine, Supervisor, User) and the trap mechanism used to handle exceptions, interrupts, and environment calls across privilege boundaries. Related Links: Platform Interrupt Architecture PMP and Isolationhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/RISC-V RISC-V - an open-standard instruction set architecture based on RISC principles, increasingly used in embedded systems for its modularity, extensibility, and royalty-free licensing. Platform Interrupt Architecture PMP and Isolation Privilege Model and Trap Handling Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/single-core-vs-multi-core-architectures/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/single-core-vs-multi-core-architectures/Single Core vs Multi-Core Architectures Single Core vs Multi-Core Architectures - comparison of single-processor and multi-processor embedded designs, including trade-offs in complexity, power, real-time behavior, and inter-core communication. Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-Vhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/trustzone-m/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/trustzone-m/TrustZone-M TrustZone-M - the Cortex-M security extension that partitions the system into Secure and Non-Secure worlds, enabling hardware-enforced isolation between trusted firmware and untrusted application code. Related Links: Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns NVIChttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/von-neumann/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/von-neumann/Von Neumann Von Neumann - a processor memory architecture where instructions and data share a single address space and bus, simplifying design at the cost of simultaneous instruction and data access. Related Links: Harvard