https://r0tbyt3.dev/tags/arm-m-profile/Recent content in Arm-M-Profile on Jesus OsegueraHugoen-ushttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/Arm M-profile Arm M-profile - the family of Arm processor cores designed for embedded and microcontroller applications, including the Cortex-M series with its NVIC, MPU, and TrustZone-M security extensions. Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns NVIC TrustZone-M Related Links: Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/boot-flow-on-cortex-m/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/boot-flow-on-cortex-m/Boot Flow on Cortex-M Boot Flow on Cortex-M - the sequence of steps from power-on through reset vector fetch, stack pointer initialization, and startup code execution that brings a Cortex-M device to its main application. Related Links: Exceptions Interruptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/exceptions/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/exceptions/Exceptions Exceptions - synchronous and asynchronous events on Cortex-M that transfer control to exception handlers, including faults, SVC calls, and system-level exceptions. Related Links: Boot Flow on Cortex-M Interruptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/interruptions/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/interruptions/Interruptions Interruptions - hardware interrupt signals on Cortex-M that trigger IRQ handlers via the NVIC, including priority management, nesting, and tail-chaining behavior. Related Links: Boot Flow on Cortex-M Exceptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/mpu-usage-patterns/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/mpu-usage-patterns/MPU Usage Patterns MPU Usage Patterns - common configurations of the Cortex-M Memory Protection Unit to enforce privilege separation, protect stack regions, and prevent unauthorized memory access. Related Links: Boot Flow on Cortex-M Exceptions Interruptions NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/nvic/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/nvic/NVIC NVIC - the Nested Vectored Interrupt Controller on Cortex-M that manages interrupt priority, enabling, pending state, and vectored dispatch to handler functions. Related Links: Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/trustzone-m/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/trustzone-m/TrustZone-M TrustZone-M - the Cortex-M security extension that partitions the system into Secure and Non-Secure worlds, enabling hardware-enforced isolation between trusted firmware and untrusted application code. Related Links: Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns NVIC