https://r0tbyt3.dev/tags/embedded-systems/Recent content in Embedded-Systems on Jesus OsegueraHugoen-ushttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/accessing-memory-mapped-registers-with-pointers/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/accessing-memory-mapped-registers-with-pointers/Accessing Memory-Mapped Registers with Pointers Accessing Memory-Mapped Registers with Pointers - technique for directly reading and writing hardware registers by casting their addresses to typed pointer types in C. Related Links: Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/Arm M-profile Arm M-profile - the family of Arm processor cores designed for embedded and microcontroller applications, including the Cortex-M series with its NVIC, MPU, and TrustZone-M security extensions. Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns NVIC TrustZone-M Related Links: Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/bitwise-operators-and-bit-manipulation-techniques/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/bitwise-operators-and-bit-manipulation-techniques/Bitwise Operators and Bit Manipulation Techniques Bitwise Operators and Bit Manipulation Techniques - operators and patterns for reading, setting, clearing, and toggling individual bits in registers and data fields. Related Links: Accessing Memory-Mapped Registers with Pointers Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/board-bring-up-and-hardware-validation/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/board-bring-up-and-hardware-validation/Board Bring-Up and Hardware Validation Board Bring-Up and Hardware Validation - process of verifying a newly assembled PCB by systematically testing power rails, clocks, communication interfaces, and peripherals. Related Links: Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/boot-flow-on-cortex-m/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/boot-flow-on-cortex-m/Boot Flow on Cortex-M Boot Flow on Cortex-M - the sequence of steps from power-on through reset vector fetch, stack pointer initialization, and startup code execution that brings a Cortex-M device to its main application. Related Links: Exceptions Interruptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/exploits/buffer-overflow/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/exploits/buffer-overflow/Buffer Overflow Buffer Overflow - vulnerability caused by writing beyond the bounds of a fixed-size buffer, potentially overwriting control data or enabling arbitrary code execution. Related Links: Firmware Exploitation Network Attacks Physical Attacks Side-Channel Attackshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/bus-fabrics-and-on-chip-interconnects/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/bus-fabrics-and-on-chip-interconnects/Bus Fabrics and On-Chip Interconnects Bus Fabrics and On-Chip Interconnects - the internal communication infrastructure of a SoC that connects the CPU, memory, and peripherals, including AHB, APB, AXI, and crossbar fabrics. Related Links: Arm M-profile CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/C Language for Embedded Systems C Language for Embedded Systems - the programming language commonly used for developing software for embedded systems due to its efficiency and low-level control. (Note: This is different from application-level C programming, which may involve higher-level abstractions and libraries.) Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentals Related Links: Embedded Systems Architectures Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Hardware Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/cables-connectors-and-physical-interfaces/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/cables-connectors-and-physical-interfaces/Cables, Connectors, and Physical Interfaces Cables, Connectors, and Physical Interfaces - physical interconnects used to connect embedded boards to peripherals, power supplies, and debug tools. Related Links: Board Bring-Up and Hardware Validation Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/can-bus/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/can-bus/CAN Bus CAN Bus - multi-master serial bus protocol used in automotive and industrial embedded systems for reliable, prioritized message exchange. Related Links: I2C Monodon Firmware SPI UARThttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/clocking-and-reset-circuits/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/clocking-and-reset-circuits/Clocking and Reset Circuits Clocking and Reset Circuits - oscillators, PLLs, and reset logic that establish and maintain the timing and initialization state of a microcontroller. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/compiler-optimization-behavior-and-volatile-fixes/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/compiler-optimization-behavior-and-volatile-fixes/Compiler Optimization Behavior and volatile Fixes Compiler Optimization Behavior and volatile Fixes - how compilers reorder or eliminate memory accesses and how the volatile qualifier prevents such optimizations on hardware-mapped variables. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/complex-const-and-volatile-combinations/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/complex-const-and-volatile-combinations/Complex const and volatile Combinations Complex const and volatile Combinations - combined use of const and volatile qualifiers to model read-only hardware registers and shared data in embedded C. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/control-flow-for-firmware/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/control-flow-for-firmware/Control Flow for Firmware Control Flow for Firmware - use of conditionals, loops, and switch statements in firmware, including considerations for deterministic execution and avoiding undefined behavior. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/cooperative-scheduling/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/cooperative-scheduling/Cooperative Scheduling Cooperative Scheduling - execution model where tasks voluntarily yield the processor, requiring explicit hand-off points to ensure fairness and responsiveness. Related Links: Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/CPU Core Concepts CPU Core Concepts - fundamental principles of processor design relevant to embedded systems, including instruction set architectures, pipeline stages, and privilege levels. ISA Privilege Levels Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/data-types-variables-and-storage-class-specifiers/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/data-types-variables-and-storage-class-specifiers/Data Types, Variables, and Storage Class Specifiers Data Types, Variables, and Storage Class Specifiers - fixed-width integer types, alignment, storage classes (auto, static, extern, register), and their impact on memory layout. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/debug-and-programming-hardware/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/debug-and-programming-hardware/Debug and Programming Hardware Debug and Programming Hardware - tools and circuits used to flash firmware and debug running code, including JTAG, SWD, and debug adapters. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/defensive-c-patterns-for-vulnerability-prevention/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/defensive-c-patterns-for-vulnerability-prevention/Defensive C Patterns for Vulnerability Prevention Defensive C Patterns for Vulnerability Prevention - coding practices that reduce common firmware vulnerabilities such as buffer overflows, integer wrapping, and uninitialized memory use. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/digital-and-analog-peripherals/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/digital-and-analog-peripherals/Digital and Analog Peripherals Digital and Analog Peripherals - microcontroller-integrated or external digital and analog devices such as GPIOs, ADCs, DACs, and timers. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/elf-file-format-symbols-sections-and-segments/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/elf-file-format-symbols-sections-and-segments/ELF File Format, Symbols, Sections, and Segments ELF File Format, Symbols, Sections, and Segments - structure of ELF binaries produced by the toolchain, including .text, .data, .bss sections and symbol table layout. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/Embedded Systems Map Embedded Systems - design, development, and maintenance of specialized computing systems that are integrated into larger devices or systems to perform specific functions. Architectures C Language Communication Protocols Execution Models Exploits Hardware Runtime View STM32 Microcontrollers Related Links: Backend Engineering Cybersecurity DevOps and Platform Engineering Homehttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/Embedded Systems Architectures Embedded Systems Architectures - the different approaches to designing and structuring embedded systems, including single-core, multi-core, and heterogeneous architectures. Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-V Single-Core vs Multi-Core Architectures Related Links: C Language for Embedded Systems Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Hardware Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/Embedded Systems Communication Protocols Embedded Systems Communication Protocols - the methods and standards used for communication between embedded systems and other devices or systems. CAN Bus I2C Monodon Firmware SPI UART Related Links: C Language for Embedded Systems Embedded Systems Architectures Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Hardware Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/Embedded Systems Execution Models Embedded Systems Execution Models - the different approaches to managing and executing code in embedded systems, including polling, interrupt-driven, and real-time operating system (RTOS) based models. Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handling Related Links: C Language for Embedded Systems Embedded Systems Architectures Embedded Systems Communication Protocols Embedded Systems Exploits Embedded Systems Hardware Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/exploits/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/exploits/Embedded Systems Exploits Embedded Systems Exploits - the methods and techniques used to identify and exploit vulnerabilities in embedded systems. Buffer Overflow Firmware Exploitation Network Attacks Physical Attacks Side-Channel Attacks Related Links: C Language for Embedded Systems Embedded Systems Architectures Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Hardware Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/Embedded Systems Hardware Embedded Systems Hardware - the physical components and architecture of embedded systems, including microcontrollers, memory, and peripheral devices. Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shifting Related Links: C Language for Embedded Systems Embedded Systems Architectures Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Runtime View STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/event-driven-and-state-machine-models/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/event-driven-and-state-machine-models/Event-Driven and State-Machine Models Event-Driven and State-Machine Models - firmware architecture that transitions between well-defined states in response to hardware events or software signals. Related Links: Cooperative Scheduling Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/exceptions/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/exceptions/Exceptions Exceptions - synchronous and asynchronous events on Cortex-M that transfer control to exception handlers, including faults, SVC calls, and system-level exceptions. Related Links: Boot Flow on Cortex-M Interruptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/failure-recovery-models/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/failure-recovery-models/Failure Recovery Models Failure Recovery Models - strategies for detecting and recovering from runtime errors, watchdog timeouts, and unexpected system states in embedded firmware. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/exploits/firmware-exploitation/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/exploits/firmware-exploitation/Firmware Exploitation Firmware Exploitation - techniques for identifying and exploiting vulnerabilities in embedded firmware, including reverse engineering and binary patching. Related Links: Buffer Overflow Network Attacks Physical Attacks Side-Channel Attackshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/functions-and-modular-firmware-design/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/functions-and-modular-firmware-design/Functions and Modular Firmware Design Functions and Modular Firmware Design - function declarations, calling conventions, stack usage, and techniques for organizing firmware into reusable modules. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/harvard/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/harvard/Harvard Harvard - a processor memory architecture that uses separate buses for instruction and data memory, enabling simultaneous fetches and improving throughput in embedded applications. Related Links: Von Neumannhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/heterogeneous-socs-and-co-processors/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/heterogeneous-socs-and-co-processors/Heterogeneous SoCs and Co-processors Heterogeneous SoCs and Co-processors - system-on-chip designs that integrate multiple processor types (such as Cortex-M and Cortex-A), DSPs, or hardware accelerators to balance performance and power efficiency. Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Memory Architecture Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/hybrid-polling-and-interrupt-models/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/hybrid-polling-and-interrupt-models/Hybrid Polling and Interrupt Models Hybrid Polling and Interrupt Models - combined approach that uses interrupts to flag events and polling loops to process them, balancing latency and complexity. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/i2c/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/i2c/I2C I2C - two-wire serial bus protocol for short-distance communication between a master and multiple peripheral devices sharing clock and data lines. Related Links: CAN Bus Monodon Firmware SPI UARThttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/interrupt-driven-execution/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/interrupt-driven-execution/Interrupt-Driven Execution Interrupt-Driven Execution - firmware architecture where hardware interrupt service routines respond to peripheral events asynchronously with the main execution flow. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/interruptions/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/interruptions/Interruptions Interruptions - hardware interrupt signals on Cortex-M that trigger IRQ handlers via the NVIC, including priority management, nesting, and tail-chaining behavior. Related Links: Boot Flow on Cortex-M Exceptions MPU Usage Patterns NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/isa/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/isa/ISA ISA - the Instruction Set Architecture defining the set of operations a processor can execute, including encoding formats, addressing modes, and the programmer-visible register model. Related Links: Privilege Levelshttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/isr-to-task-communication-patterns/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/isr-to-task-communication-patterns/ISR-to-Task Communication Patterns ISR-to-Task Communication Patterns - mechanisms for safely passing data and signals from interrupt service routines to application-level tasks. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/Memory Architecture Memory Architecture - the organization of instruction and data memory in embedded processors, including the distinctions between Harvard and Von Neumann architectures and their trade-offs. Harvard Von Neumann Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Power and Clock Domain Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/memory-hardware/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/memory-hardware/Memory Hardware Memory Hardware - physical memory devices used in embedded systems including Flash, SRAM, EEPROM, and external memory interfaces. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/microcontrollers-and-selection-criteria/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/microcontrollers-and-selection-criteria/Microcontrollers and Selection Criteria Microcontrollers and Selection Criteria - factors and trade-offs involved in selecting a microcontroller for an embedded application, including performance, power, and peripherals. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/monodon-firmware/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/monodon-firmware/Monodon Firmware Monodon Firmware - firmware implementation and protocol details for the Monodon communication stack. Related Links: CAN Bus I2C SPI UARThttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/mpu-usage-patterns/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/mpu-usage-patterns/MPU Usage Patterns MPU Usage Patterns - common configurations of the Cortex-M Memory Protection Unit to enforce privilege separation, protect stack regions, and prevent unauthorized memory access. Related Links: Boot Flow on Cortex-M Exceptions Interruptions NVIC TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/exploits/network-attacks/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/exploits/network-attacks/Network Attacks Network Attacks - exploitation techniques targeting network-connected embedded systems through protocol vulnerabilities, unauthenticated services, or traffic interception. Related Links: Buffer Overflow Firmware Exploitation Physical Attacks Side-Channel Attackshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/nvic/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/nvic/NVIC NVIC - the Nested Vectored Interrupt Controller on Cortex-M that manages interrupt priority, enabling, pending state, and vectored dispatch to handler functions. Related Links: Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns TrustZone-Mhttps://r0tbyt3.dev/wiki/content/embedded-systems/exploits/physical-attacks/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/exploits/physical-attacks/Physical Attacks Physical Attacks - hardware-level attack techniques including fault injection, probe-based extraction, and physical tampering with embedded devices. Related Links: Buffer Overflow Firmware Exploitation Network Attacks Side-Channel Attackshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/platform-interrupt-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/platform-interrupt-architecture/Platform Interrupt Architecture Platform Interrupt Architecture - the RISC-V PLIC and CLINT interrupt controllers that route external and timer interrupts to harts with configurable priority and threshold settings. Related Links: PMP and Isolation Privilege Model and Trap Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/pmp-and-isolation/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/pmp-and-isolation/PMP and Isolation PMP and Isolation - the RISC-V Physical Memory Protection unit used to restrict memory access by privilege level, enabling isolation between firmware components and sandboxing of untrusted code. Related Links: Platform Interrupt Architecture Privilege Model and Trap Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/pointers-and-casting-in-embedded-c/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/pointers-and-casting-in-embedded-c/Pointers and Casting in Embedded C Pointers and Casting in Embedded C - pointer arithmetic, void pointers, and type casting used to access hardware registers and manipulate raw memory. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/power-and-clock-domain-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/power-and-clock-domain-architecture/Power and Clock Domain Architecture Power and Clock Domain Architecture - the organization of clock trees and power domains within a SoC, including clock gating, domain isolation, and power management controller design. Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture RISC-V Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/power-regulation-and-conversion/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/power-regulation-and-conversion/Power Regulation and Conversion Power Regulation and Conversion - circuits that convert and regulate supply voltages for embedded hardware, including LDOs, buck converters, and boost converters. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Sources and Power Budgeting Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/power-sources-and-power-budgeting/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/power-sources-and-power-budgeting/Power Sources and Power Budgeting Power Sources and Power Budgeting - battery types, energy harvesting sources, and methods for estimating and managing total system power consumption. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Sensors, Actuators, and Driver Components Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/power-aware-execution-strategies/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/power-aware-execution-strategies/Power-Aware Execution Strategies Power-Aware Execution Strategies - techniques for reducing energy consumption through sleep modes, clock gating, and workload scheduling. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/preemptive-rtos-scheduling/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/preemptive-rtos-scheduling/Preemptive RTOS Scheduling Preemptive RTOS Scheduling - real-time operating system model where the scheduler can interrupt a running task to give the CPU to a higher-priority task. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/privilege-levels/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/cpu-core-concepts/privilege-levels/Privilege Levels Privilege Levels - the hardware-enforced execution modes (such as privileged and unprivileged) that control access to protected instructions, registers, and memory regions. Related Links: ISAhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/privilege-model-and-trap-handling/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/privilege-model-and-trap-handling/Privilege Model and Trap Handling Privilege Model and Trap Handling - the RISC-V privilege levels (Machine, Supervisor, User) and the trap mechanism used to handle exceptions, interrupts, and environment calls across privilege boundaries. Related Links: Platform Interrupt Architecture PMP and Isolationhttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/real-time-constraints-latency-and-jitter/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/real-time-constraints-latency-and-jitter/Real-Time Constraints, Latency, and Jitter Real-Time Constraints, Latency, and Jitter - timing requirements for embedded systems including deadlines, worst-case execution times, and sources of scheduling variance. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Shared-State Synchronization and Concurrency Safety Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/register-definitions-with-c-structures/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/register-definitions-with-c-structures/Register Definitions with C Structures Register Definitions with C Structures - use of structs and bitfields to model memory-mapped peripheral register blocks with named field access. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/relocation-linking-literal-pools-and-veneers/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/relocation-linking-literal-pools-and-veneers/Relocation, Linking, Literal Pools, and Veneers Relocation, Linking, Literal Pools, and Veneers - how the linker resolves symbol references, manages literal pools, and inserts veneers for out-of-range branches. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Structures, Bitfields, Unions, and Bit Extraction Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/RISC-V RISC-V - an open-standard instruction set architecture based on RISC principles, increasingly used in embedded systems for its modularity, extensibility, and royalty-free licensing. Platform Interrupt Architecture PMP and Isolation Privilege Model and Trap Handling Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture Single Core vs Multi-Core Architectureshttps://r0tbyt3.dev/wiki/content/embedded-systems/runtime-view/runtime-memory-management/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/runtime-view/runtime-memory-management/Runtime Memory Management Runtime Memory Management - strategies for allocating, using, and freeing memory during firmware execution, including static allocation and heap management. Related Links: Task Scheduling and Context Switchinghttps://r0tbyt3.dev/wiki/content/embedded-systems/runtime-view/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/runtime-view/Runtime View of Embedded Systems Runtime View of Embedded Systems - the perspective of how an embedded system behaves during execution, including the management of resources, task scheduling, and interaction with the hardware. Runtime Memory Management Task Scheduling and Context Switching Related Links: C Language for Embedded Systems Embedded Systems Architectures Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Hardware STM32 Microcontrollershttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/sensors-actuators-and-driver-components/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/sensors-actuators-and-driver-components/Sensors, Actuators, and Driver Components Sensors, Actuators, and Driver Components - input transducers, output actuators, and the driver circuits that interface them to a microcontroller. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Signal Integrity, Protection, and Level Shiftinghttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/shared-state-synchronization-and-concurrency-safety/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/shared-state-synchronization-and-concurrency-safety/Shared-State Synchronization and Concurrency Safety Shared-State Synchronization and Concurrency Safety - techniques for safely sharing data between tasks or ISRs, including atomic operations, mutexes, and critical sections. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Superloop Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/exploits/side-channel-attacks/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/exploits/side-channel-attacks/Side-Channel Attacks Side-Channel Attacks - exploitation of information leaked through power consumption, electromagnetic emissions, timing variations, or other physical side channels. Related Links: Buffer Overflow Firmware Exploitation Network Attacks Physical Attackshttps://r0tbyt3.dev/wiki/content/embedded-systems/hardware/signal-integrity-protection-and-level-shifting/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/hardware/signal-integrity-protection-and-level-shifting/Signal Integrity, Protection, and Level Shifting Signal Integrity, Protection, and Level Shifting - techniques for maintaining clean signal transmission and protecting circuits from voltage mismatches, ESD, and noise. Related Links: Board Bring-Up and Hardware Validation Cables, Connectors, and Physical Interfaces Clocking and Reset Circuits Debug and Programming Hardware Digital and Analog Peripherals Memory Hardware Microcontrollers and Selection Criteria Power Regulation and Conversion Power Sources and Power Budgeting Sensors, Actuators, and Driver Componentshttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/single-core-vs-multi-core-architectures/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/single-core-vs-multi-core-architectures/Single Core vs Multi-Core Architectures Single Core vs Multi-Core Architectures - comparison of single-processor and multi-processor embedded designs, including trade-offs in complexity, power, real-time behavior, and inter-core communication. Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture RISC-Vhttps://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/spi/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/spi/SPI SPI - high-speed, full-duplex serial protocol for communicating with peripherals using dedicated clock, MOSI, MISO, and chip-select lines. Related Links: CAN Bus I2C Monodon Firmware UARThttps://r0tbyt3.dev/wiki/content/embedded-systems/stm32-microcontrollers/stm32-blue-pill/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/stm32-microcontrollers/stm32-blue-pill/STM32 Blue Pill STM32 Blue Pill - low-cost STM32F103-based development board commonly used for prototyping and learning embedded development with the STM32 family. Related Links: STM32L5 Serieshttps://r0tbyt3.dev/wiki/content/embedded-systems/stm32-microcontrollers/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/stm32-microcontrollers/STM32 Microcontrollers STM32 Microcontrollers - a family of 32-bit ARM Cortex-M microcontrollers designed by STMicroelectronics with a vendor-specific microcontroller architecture used in a wide range of embedded systems applications. STM32 Blue Pill STM32L5 Series Related Links: C Language for Embedded Systems Embedded Systems Architectures Embedded Systems Communication Protocols Embedded Systems Execution Models Embedded Systems Exploits Embedded Systems Hardware Embedded Systems Runtime Viewhttps://r0tbyt3.dev/wiki/content/embedded-systems/stm32-microcontrollers/stm32l5-series/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/stm32-microcontrollers/stm32l5-series/STM32L5 Series STM32L5 Series - STMicroelectronics ultra-low-power microcontroller series featuring Arm Cortex-M33 with TrustZone and advanced security features. Related Links: STM32 Blue Pillhttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/structures-bitfields-unions-and-bit-extraction/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/structures-bitfields-unions-and-bit-extraction/Structures, Bitfields, Unions, and Bit Extraction Structures, Bitfields, Unions, and Bit Extraction - aggregate data types used to model packed hardware data, protocol frames, and register overlays. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Toolchain Fundamentalshttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/superloop/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/superloop/Superloop Superloop - the simplest embedded execution model consisting of an infinite loop that polls peripherals and handles all system tasks sequentially. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Task Priorities and Deadline Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/task-priorities-and-deadline-handling/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/execution-models/task-priorities-and-deadline-handling/Task Priorities and Deadline Handling Task Priorities and Deadline Handling - assignment of execution priorities to tasks in an RTOS and strategies for meeting hard and soft timing deadlines. Related Links: Cooperative Scheduling Event-Driven and State-Machine Models Failure Recovery Models Hybrid Polling and Interrupt Models Interrupt-Driven Execution ISR-to-Task Communication Patterns Power-Aware Execution Strategies Preemptive RTOS Scheduling Real-Time Constraints, Latency, and Jitter Shared-State Synchronization and Concurrency Safety Superloophttps://r0tbyt3.dev/wiki/content/embedded-systems/runtime-view/task-scheduling-and-context-switching/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/runtime-view/task-scheduling-and-context-switching/Task Scheduling and Context Switching Task Scheduling and Context Switching - mechanisms by which an RTOS saves and restores task state to achieve multitasking on a single processor. Related Links: Runtime Memory Managementhttps://r0tbyt3.dev/wiki/content/embedded-systems/c-language/toolchain-fundamentals/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/c-language/toolchain-fundamentals/Toolchain Fundamentals Toolchain Fundamentals - components of the embedded C toolchain including the compiler, assembler, linker, and object file utilities. Related Links: Accessing Memory-Mapped Registers with Pointers Bitwise Operators and Bit Manipulation Techniques Compiler Optimization Behavior and volatile Fixes Complex const and volatile Combinations Control Flow for Firmware Data Types, Variables, and Storage Class Specifiers Defensive C Patterns for Vulnerability Prevention ELF File Format, Symbols, Sections, and Segments Functions and Modular Firmware Design Pointers and Casting in Embedded C Register Definitions with C Structures Relocation, Linking, Literal Pools, and Veneers Structures, Bitfields, Unions, and Bit Extractionhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/trustzone-m/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/arm-m-profile/trustzone-m/TrustZone-M TrustZone-M - the Cortex-M security extension that partitions the system into Secure and Non-Secure worlds, enabling hardware-enforced isolation between trusted firmware and untrusted application code. Related Links: Boot Flow on Cortex-M Exceptions Interruptions MPU Usage Patterns NVIChttps://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/uart/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/communication-protocols/uart/UART UART - asynchronous serial communication protocol for point-to-point data exchange between microcontrollers and peripherals. Related Links: CAN Bus I2C Monodon Firmware SPIhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/von-neumann/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/memory-architecture/von-neumann/Von Neumann Von Neumann - a processor memory architecture where instructions and data share a single address space and bus, simplifying design at the cost of simultaneous instruction and data access. Related Links: Harvard