https://r0tbyt3.dev/tags/risc-v/Recent content in Risc-V on Jesus OsegueraHugoen-ushttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/platform-interrupt-architecture/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/platform-interrupt-architecture/Platform Interrupt Architecture Platform Interrupt Architecture - the RISC-V PLIC and CLINT interrupt controllers that route external and timer interrupts to harts with configurable priority and threshold settings. Related Links: PMP and Isolation Privilege Model and Trap Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/pmp-and-isolation/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/pmp-and-isolation/PMP and Isolation PMP and Isolation - the RISC-V Physical Memory Protection unit used to restrict memory access by privilege level, enabling isolation between firmware components and sandboxing of untrusted code. Related Links: Platform Interrupt Architecture Privilege Model and Trap Handlinghttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/privilege-model-and-trap-handling/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/privilege-model-and-trap-handling/Privilege Model and Trap Handling Privilege Model and Trap Handling - the RISC-V privilege levels (Machine, Supervisor, User) and the trap mechanism used to handle exceptions, interrupts, and environment calls across privilege boundaries. Related Links: Platform Interrupt Architecture PMP and Isolationhttps://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/Mon, 01 Jan 0001 00:00:00 +0000https://r0tbyt3.dev/wiki/content/embedded-systems/architectures/risc-v/RISC-V RISC-V - an open-standard instruction set architecture based on RISC principles, increasingly used in embedded systems for its modularity, extensibility, and royalty-free licensing. Platform Interrupt Architecture PMP and Isolation Privilege Model and Trap Handling Related Links: Arm M-profile Bus Fabrics and On-Chip Interconnects CPU Core Concepts Heterogeneous SoCs and Co-processors Memory Architecture Power and Clock Domain Architecture Single Core vs Multi-Core Architectures